Hardware-Based Floating-Point Design Flow

Floating-point processing utilizes a format defined in IEEE 754, and is supported by microprocessor architectures. However, the IEEE 754 format is inefficient to implement in hardware, and floating-point processing is not supported in VHDL or Verilog. Newer versions, such as SystemVerilog, allow floating-point variables, but industry-standard synthesis tools do not support floating-point technology. This paper describes a new approach which efficiently implements floating-point data processing in hardware architectures, specifically FPGAs. This allows for extremely high rates of floating-point processing, of at least 1 TeraFLOPS in a single FPGA die, and with significantly better power efficiency than the microprocessor-based alternatives. As senior DSP technical marketing manager, Michael Parker is responsible for Altera's DSP-related IP, and is also involved in optimizing FPGA architecture planning for DSP applications. Mr. Parker joined Altera in January 2007, and has over 20 years of DSP wireless engineering design experience with Alvarion, Soma Networks, TCSI, Stanford Telecom, and several startup companies.